Some electronic applications employ delay circuits or circuitry where it is desirable to have consistent signal delays. For example, in a communication device, a delay circuit can be used to compensate for large timing skews imparted on a signal as a result of the signal passing through a communication channel and front-end analog circuits. In general, higher performance can be achieved if the delay imparted on a signal remains relatively constant in spite of variations in process, voltage, and temperature (PVT) that may otherwise affect the operation of the circuit. In some of these applications, it is also desirable for the circuitry to have fast turn-on and turn-off times and low overhead (e.g., in terms of latency and power consumption). For example, in a high speed serial communication circuit that employs burst mode, the circuit may be turned-on during a communication burst and turned-off otherwise. In view of the above, it is desirable for some applications for circuits such a delay circuits to have (1) a high tolerance to PVT variations, (2) low power consumption, and (3) a fast turn-on time.
FIG. 1 illustrates a conventional delay circuit 100 that employs fixed tail bias currents IB1 and IB2 for PVT compensation. Here, a differential input signal IN_P and IN_N drives a first transistor pair 102, resulting in a delayed differential output signal OUT_P and OUT_N generated by a second transistor pair 104. However, the delay circuit 100 is not a true digital logic cell since the input and output signals do not swing from rail-to-rail due to the current sources 106 and the load resistors 108. Moreover, the on-chip current sources 106 are calibrated whenever the delay circuit 100 is powered-on. The resulting calibration time for the current sources 106 increases the overhead associated with the delay circuit 100.
FIG. 2 illustrates another conventional delay circuit 200 that employs a feedback loop 202 for PVT compensation. The feedback loop 202 controls direct current (DC) voltage levels at back-gates, also known as body bias terminals (e.g., body bias terminals 204), of pairs of NMOS and PMOS transistors (e.g., transistors 206) to adjust the delay imparted on an input clock CLK_REF by the NMOS and PMOS transistors. In the delay circuit 200, a comparator 208 compares the input clock CLK_REF with the output (delayed) clock OUT and generates a signal that is proportional to the delay. Based on this signal, a decoder 210 and bias generators 212 cooperate to generate bias voltages Vbp and Vbn that are fed back to the body bias terminals 204 of the NMOS and PMOS transistors. In practice, however, the feedback loop 202 has a limited bandwidth. Consequently, the delay circuit 200 has a relatively a long turn-on time and turn-off time. In addition, the feedback circuit has relatively high power consumption due to the use of the comparator 208, the decoder 210, and the bias generators 212.
Other types of conventional delay circuits employ on-chip delay calibration such as system calibration. However, system level calibration is generally calibrated for a particular corner, temperature, and voltage (e.g., Vdd) condition. Moreover, these delay circuits are calibrated every time the delay circuit is turned-on. Consequently, these types of delay circuits do not provide sufficiently fast turn-on and turn-off times (e.g., sufficient for high speed burst mode communication) and have relatively high overhead. Consequently, there is a need for improved PVT compensation for delay circuits and other types of circuits.